1. Field of the Invention
The present invention relates to logic circuits of the type comprising differential stages operating in linear mode, such as Emitter-Coupled Logic (ECL) circuits.
2. Discussion of the Related Art
ECL circuits are ones of the fastest logic circuits. To reach a high operation speed, ECL circuits are designed so that their bipolar transistors never go to saturation mode. Bipolar transistors saturate when their collector-emitter voltage Vce is lower than their base-emitter voltage Vbe. In such an instance, the base has a substantially higher capacity as compared to an instance in which the transistor operates in the linear mode, which causes conventional bipolar circuits to be slow. To prevent transistors from saturating, the transistors are connected in differential stages, hence the "emitter-coupled" terminology. Thus, differential signals are generally processed by ECL circuits, each component of a differential signal being applied to a respective input of a differential stage.
FIG. 1 represents an exemplary conventional ECL circuit, in this example a multiplexer. All the transistors of the ECL circuits are of the bipolar NPN-type. A first complementary signal A/A* is applied to the inputs of a first differential stage formed by a pair of transistors Q1 and Q2. The collectors of transistors Q1 and Q2 are connected to a high supply voltage Vcc through respective resistors Rc. The resistors Rc are mounted in the branches of the differential stage Q1, Q2. A second differential signal B/B* is applied to the inputs of a differential stage formed by a pair of transistors Q3 and Q4. The two branches of stage Q3, Q4 are connected to the branches of stage Q1, Q2, respectively.
Stages Q1, Q2, and Q3, Q4 are respectively connected in the branches of a differential stage formed by a pair of transistors Q5 and Q6, i.e., the collector of transistor Q5 is connected to the emitters of transistors Q1 and Q2, and the collector of transistor Q6 is connected to the emitters of transistors Q3 and Q4. Stage Q8, Q6 is biased through a supply source formed by a transistor Q7 whose emitter is connected to a low supply voltage GND (ground) through a resistor Re1, and whose collector is connected to the emitters of transistors Q5 and Q6. A reference voltage Vr applied to the base of transistor Q7 determines the biasing current of stage Q5, Q6. A differential selection signal S/S* is applied to the inputs of stage Q5, Q6 through follower-connected transistors Q8 and Q9.
The output of the logic circuit is a differential signal D/D* drawn from the branches of stage Q1, Q2 through follower transistors Q10 and Q11.
The follower transistors Q8-Q11 are respectively biased by transistors Q12-Q15 that are connected to emitter resistors (Re2 for transistors Q12, Q13 and Re3 for transistors Q14 and Q15) like transistor Q7.
The multiplexer operates as follows. If the differential signal S/S* is high (i.e., components S and S* are respectively high and low), transistor Q5 is conductive and transistor Q6 is blocked. Stage Q3, Q4 is then inactive; only stage Q1, Q2 imposes the value of signal A/A* to the output D/D* Conversely, if signal S/S* is low, signal B/B* ms present at output D/D*.
The follower transistors Q8 and Q9 are necessary to prevent transistors Q5 and Q6 from saturating. For example, if components A and S are at the same state, the collector and base voltages of transistor Q5 are equal, which ensures that the collector-emitter voltage of transistor Q5 is at least equal to the base-emitter voltage Vbe of transistor Q5. In the absence of the follower transistor Q8, the collector-emitter voltage of transistor Q5 would be substantially zero, causing transistor Q5 to saturate.
ECL signals have a small range, i.e., the voltage difference between the high state and the low state of a component of an ECL signal is small. This small range, approximately 0.5 volt, increases the rapidity of the logic circuit by decreasing the charge and discharge energy of any parasitic capacitances.
To determine the change over time of an ECL signal the emitter voltage (D*) of transistor Q10, for example, is considered. If transistors Q1 and Q4 are blocked, this voltage is substantially equal to Vcc-Vbe. If transistors Q1 and Q5 are conductive, the voltage drops by a value Vs, corresponding to the ECL range, equal to the product of the current in transistor Q7 by the resistance Rc. Accordingly, the voltage at the output D* varies from Vcc-Vbe to Vcc-Vbe-Vs. The circuit of FIG. 1 is designed to be connected through one of its input (A/A* B/B* S/S*) to the output (D/D*) of another similar circuit. The range Vs being fixed (approximately 0.5 volt), the voltage Vcc should be high enough so that the minimum value of the output of the other circuit does not cause transistors Q1, Q5, Q7 or Q8, Q5, Q7, for example, to saturate. Thus, the minimum voltage of output D* is equal to the sum of three voltages Vbe (of transistors Q1 or Q8, and Q5 and Q7, for example) and of a voltage Vr-Vbe occurring across the emitter resistor Re of transistor Q7. Therefore, the minimum voltage is 2Vbe+Vr. Therefore, the supply voltage Vcc should be such that: EQU Vcc-Vbe-Vs&gt;2Vbe+Vr.
For typical values Vs=0.5, Vbe=0.9, Vr=1.2, voltage Vcc should be at least equal to to 4.4 volts. An ECL circuit is typically supplied at 5 volts.
A drawback of ECL circuits is their high current consumption due to the fact that the currents supplied by the current sources are always consumed by the follower transistors or by either one of the other branches of a differential stage. If the supply voltage Vcc could be decreased, the current consumption would be decreased by the same extent.